Increasing Resistance Against Power Analysis Attacks Using Dual Key Scheme
Abstract
Execution of a mathematically secure encryption algorithm on hardware is known to leak certain information to the side channels of the hardware. These side channels include current consumed from power supply and electromagnetic radiation emitted from cryptographic hardware. The information thus leaked can be utilized to mount an attack to reveal secret information about the algorithm (e.g. encryption key). This method of extracting the information is broadly classified as “Side Channel Attacks”. A type of side channel attack called “Power Analysis” utilizes the power/current consumed information as a source of information leakage. Several measures including “hiding” have been proposed to counter these attacks. These counter measures are based upon inserting randomness or consuming nearly constant current thus reducing the value of this information. In this research, we propose a new hiding countermeasure which uses dual keys to perform cryptographic operations. This method cannot be bypassed by increasing the number of traces.References
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Koblitz, N., Elliptic curve cryptosystems, Mathematics of Computation 48 (1987) 203– 209.
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Kocher,P. C., Jae, J., Jun, B., Differential Power Analysis, in: Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology, pp. 388–397.
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Xilinx XPOWERwww.xilinx.com/products/ design_tools/logic_design/verification/xpower.h tml last accessed October 19th 2014
Digital Integrated Circuits: A Design Perspective, Prentice Hall, 1996.
Power Analysis Attacks: Revealing the Secrets of Smart Cards, Springer, 2007.
Tiri, K., Verbauwhede, I., A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation, in: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition(DATE), pp. 246– 251.
Bo, Y., Xiangyu, L., Cong, C., Yihe, S., Liji, W., Xiangmin, Z., An AES Chip with DPA resistance using hardware-based random order execution, Journal of Semiconductors 33 (2012) 065009.
Medeiros, S. F., The Schedulability of AES as a Countermeasure against Side Channel Attacks, in: Security, Privacy, and Applied Cryptography Engineering, 2012, pp. 16–31.
Zafar, Y., Har, D., A Novel Countermeasure to Resist Side Channel Attacks on FPGA Implementations, International Journal On Advances in Security 2 (2009).
Liu, P.C., Chang, H.C., Lee, C.Y., A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine, IEEE Transactions on Circuits and Systems II: Express Briefs 59 (2012) 103–107.
Yang, S., Wolf, W., Vijaykrishnan, N., Serpanos, D. N., Xie, Y., Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach, in: Proceedings of the conference on Design, Automation and Test in Europe, pp. 64–69.
Bucci, M., Luzzi, R., Guglielmo, M., letti, A. T., A Countermeasure Against Differential Power Analysis Based on Random Delay Insertion, in: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3547–3550.
Ratanpal, G. B., Williams, R. D., Blalock, T. N., An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks, IEEE Transactions on Dependable and Secure Computing 1 (2004) 179–189.
Standaert, O.X., Peeters, E., Rouvroy, G., Quisquater J.J., An Overview of Power Analysis Attacks Against Field Programmable Gate Arrays, Proceedings Of the IEEE 94 (2006) 382–394.
Amaar, A., Ashour, I., Shiple, M., Efficient Implementation of AES Algorithm Immune to DPA Attack, in: Proceedings of 14th international Conference on Modelling and Simulation, pp. 396–401.
Strachacki, M., Szczepanski, S., Implementation of AES Algorithm Resistant to Differential Power Analysis, in: Proceedings of 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 214–217.
TEMPEST: A signal problem https:// www.nsa.gov/public_info/_files/cryptologic_sp ectrum/tempest.pdf last accessed October 5th 2014
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Published
2016-06-22
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Section
Electrical Engineering and Computer Science
